Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its stored data for some extended period without the application of power. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR Flash and NAND Flash. The designation is derived from the logic used to read the devices. FIG. 1 illustrates a NAND type flash memory array architecture 100 wherein the memory cells 102 of the memory array are logically arranged in an array of rows and columns. In a conventional NAND Flash architecture, “rows” refers to memory cells having commonly coupled control gates 120, while “columns” refers to memory cells coupled as a particular NAND string 108, for example. The memory cells 102 of the array are arranged together in strings (e.g., NAND strings), typically of 8, 16, 32, or more each. Each memory cell of a string are connected together in series, source to drain, between a source line 114 and a data line 116, often referred to as a bit line. The array is accessed by a row decoder (not shown) activating a logical row of memory cells by selecting a particular access line, often referred to as a word line, such as WL7-WL0 1187-1180, for example. Each word line is coupled to the control gates of a row of memory cells. Bit lines BL1-BL4 11614 can be driven high or low depending on the type of operation being performed on the array. These bit lines BL1-BL4 11614 are coupled to sense devices (e.g., sense amplifiers) 130 that detect the state of a target memory cell by sensing voltage or current on a particular bit line 116, for example. As is known to those skilled in the art, the number of word lines and bit lines might be much greater than those shown in FIG. 1.
Memory cells 102 can be configured as what are known in the art as Single Level Memory Cells (SLC) or Multilevel Memory Cells (MLC). SLC and MLC memory cells assign a data state (e.g., as represented by one or more bits) to a specific range of threshold voltages (Vt) stored on the memory cells. Single level memory cells (SLC) permit the storage of a single binary digit (e.g., bit) of data on each memory cell. Meanwhile, MLC technology permits the storage of two or more binary digits per cell (e.g., 2, 4, 8, 16 bits), depending on the quantity of Vt ranges assigned to the cell and the stability of the assigned Vt ranges during the lifetime operation of the memory cell. The number of Vt ranges (e.g., levels), used to represent a bit pattern comprised of N-bits is 2N, where N is an integer. For example, one bit may be represented by two ranges, two bits by four ranges, three bits by eight ranges, etc. MLC memory cells may store even or odd numbers of bits on each memory cell. A common naming convention is to refer to SLC memory as MLC (two level) memory as SLC memory utilizes two Vt ranges in order to store one bit of data as represented by a 0 or a 1, for example. MLC memory configured to store two bits of data can be represented by MLC (four level), three bits of data by MLC (eight level), etc.
FIG. 2 illustrates an example of Vt ranges 200 for a MLC (four level) (e.g., 2-bit) memory cell. For example, a memory cell might be programmed to a Vt that falls within one of four different Vt ranges 202-208 of 200 mV, each being used to represent a data state corresponding to a bit pattern comprised of two bits. Typically, a dead space 210 (e.g., sometimes referred to as a margin and may have a range of 200 mV to 400 mV) is maintained between each range 202-208 to keep the ranges from overlapping. As an example, if the voltage stored on a memory cell is within the first of the four Vt ranges 202, the cell in this case is storing a logical ‘11’ state and is typically considered the erased state of the cell. If the voltage is within the second of the four Vt ranges 204, the cell in this case is storing a logical ‘10’ state. A voltage in the third Vt range 206 of the four Vt ranges would indicate that the cell in this case is storing a logical ‘00’ state. Finally, a Vt residing in the fourth Vt range 208 indicates that a logical ‘01’ state is stored in the cell.
Memory cells are typically programmed using erase and programming cycles. For example, memory cells of a particular block of memory cells are first erased and then selectively programmed. For a NAND array, a block of memory cells is typically erased by grounding all of the word lines in the block and applying an erase voltage to a semiconductor substrate on which the block of memory cells are formed, and thus to the channels of the memory cells, in order to remove charges which might be stored on the charge storage structures (e.g., floating gates or charge traps) of the block of memory cells. This typically results in the Vt of memory cells residing in the Vt range 202 (e.g., erased state) of FIG. 2, for example.
Programming typically involves applying one or more programming pulses to a selected word line (e.g., WL4 1184) and thus to the control gate of each memory cell 1201-1204 coupled to the selected word line. Typical programming pulses start at or near 15V and tend to increase in magnitude during each programming pulse application. While the program voltage (e.g., programming pulse) is applied to the selected word line, a potential, such as a ground potential, is applied to the substrate, and thus to the channels of these memory cells, resulting in a charge transfer from the channel to the storage structures of memory cells targeted for programming. More specifically, the storage structures are typically charged through direct injection or Fowler-Nordheim tunneling of electrons from the channel to the storage structure, resulting in a Vt typically greater than zero in a programmed state, such as in Vt ranges 204-208 of FIG. 2, for example. In addition, an inhibit voltage is typically applied to bit lines not coupled to a NAND string containing a memory cell that is targeted (e.g., selected) for programming. Typically a verify operation is performed following each applied programming pulse to determine if the selected memory cells have achieved their target (e.g., intended) programmed state. A verify operation generally includes performing a sense operation to determine if a threshold voltage of a memory cell has reached a particular target value.
Typically, alternating bit lines are enabled 1161,1163 and/or inhibited 1162,1164 during a programming (e.g., write) and/or a read operation performed on a selected row of memory cells 120. This is illustrated by the solid and dashed circles shown around memory cells 120, for example. During a typical programming operation, an effect which is known as program disturb can occur where some memory cells coupled to the selected word line may reach their target threshold voltage before other memory cells coupled to the same word line reach their target threshold voltages. This condition is especially likely to occur in MLC memory. For example, one or more memory cells of a particular row might have a target threshold voltage within range 204 and others may have a target threshold voltage within range 208, for example. Thus it is possible that memory cells having a target threshold voltage within range 208 will require additional programming pulses after the memory cells having a target threshold voltage within range 204 have completed programming, for example.
The continued application of programming pulses to a selected word line (such as to complete programming of one or more memory cells of a row) can cause these program disturb issues. This is because memory cells which have achieved their target programmed states and are inhibited from programming can still experience a shift in their threshold voltage due to the continued application of programming pulses to the selected word line, for example.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present disclosure, there is a need in the art for alternate programming methods for memory devices.